SERDES Channel Design

SERDES Channel Design

HyperLynx SERDES Channel Design supports frequency-domain, time-domain, Channel Operating Margin (COM), and JCOM pre- and post-route analysis for over 35 different popular protocols.

Serial link analysis with HyperLynx

Beyond the design-specific technical challenges associated with designing and verifying serial link interconnect, hardware designers face standards-related complexity. There are more than 200 different SerDes protocols and variants, making it difficult for designers to understand more than a few. HyperLynx Compliance Analysis automatically configures analysis based on the selected protocol so users don’t have to master all of the details.
Benefits of HyperLynx serial link analysis
Some of the many benefits of using HyperLynx for SerDes channel analysis include:

Intelligent, automatic channel extractions

Interface-level channel compliance verification

Pre-Layout design exploration and optimization.

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KEY TECHNOLOGIES

Comprehensive SERDES Channel Design Support

HyperLynx delivers advanced tools for optimizing SERDES design projects.

Comprehensive SERDES support

Comprehensive reporting and compliance plots includes FastEye diagram analysis, S-parameter simulation, and BER prediction.

Integrated full-wave 3D electromagnetic field solver

HyperLynx SI makes it easy to manage detailed structure analysis (including differential vias).

IBIS-AMI Analysis

HyperLynx eliminates the time spent reading and the training needed to understand complex and sometimes obscure SERDES specifications. With the use of behavioral models, simulations are easier to set up and run faster than when IBIS-AMI models are used.

Protocol-specific Compliance Analysis

Protocol-specific compliance analysis eliminates the time spent reading and the training needed to understand complex and sometimes obscure SERDES specifications. With the use of behavioral models, simulations are easier to set up and run faster than when IBIS-AMI models are used.

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